1. Field of the Invention
The present invention relates to the field of computer systems. In particular, the present invention relates to scalability of cache memory of a computer system.
2. Background Information
As microprocessor technology continues to evolve in a faster and faster pace, purchasers of microprocessor based computer systems demand better performance scalability from the system manufacturers to protect their investment. A particular aspect of performance scalability is cache scalability. In addition to the traditional scalability in size, with the emergence of burst cache SRAM, purchasers of these systems also desire being able to upgrade from the slower performance asynchronous cache SRAM to the higher performance burst cache SRAM.
However, the manner in which addresses are provided to asynchronous cache SRAM is different from the manner addresses are provided to burst cache SRAM. From the system/component manufacturer's perspective, it would be a big cost advantage to be able to support either type of cache SRAM with the same basic hardware.
As will be disclosed in more detail below, the present invention provides a method and apparatus for removably connecting either asynchronous or burst cache SRAM to a computer system that achieves these and other desired results.